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MM80C95 * MM80C97 * MM80C98 3-STATE Hex Buffers * 3-STATE Hex Inverters
October 1987 Revised January 1999
MM80C95 * MM80C97 * MM80C98 3-STATE Hex Buffers * 3-STATE Hex Inverters
General Description
The MM80C95, MM80C97 and MM80C98 gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. The MM80C95 and the MM80C97 convert CMOS or TTL outputs to 3-STATE outputs with no logic inversion, the MM80C98 provides the logical opposite of the input signal. The MM80C95 has common 3-STATE controls for all six devices. The MM80C97 and the MM80C98 have two 3-STATE controls; one for two devices and one for the other four devices. Inputs are protected from damage due to static discharge by diode clamps to VCC and GND.
Features
s Wide supply voltage range: s Guaranteed noise margin: s High noise immunity: 3.0V to 15V 1.0V 0.45 VCC (typ.)
s TTL compatible: Drive 1 TTL Load
Applications
* Bus drivers: Typical propagation delay into 150 pF load is 40 ns
Ordering Code:
Order Number MM80C95N MM80C97M MM80C97N MM80C98N Package Number N16E M16A N16E N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
Pin Assignments for DIP MM80C95 MM80C97
Top View MM80C98
Top View
Top View (c) 1999 Fairchild Semiconductor Corporation DS005907.prf www.fairchildsemi.com
MM80C95 * MM80C97 * MM80C98
Schematic Diagrams
MM80C95 3-STATE
Truth Tables
MM80C95 Disable DIS1 0 0 0 1 1 Input DIS2 0 0 1 0 1 MM80C97 Disable DIS4 0 0 X 1 Input DIS2 0 0 1 X MM80C98 0 1 X X 0 1 H-z (Note 1) H-z (Note 2) Input Output 0 1 X X X 0 1 H-z H-z H-z Input Output
MM80C97 3-STATE
MM80C98 3-STATE
Disable DIS4 0 0 X 1
X = Irrelevant Note 1: Output 5-6 only Note 2: Output 1-4 only
Input DIS2 0 0 1 X
Input 0 1 X X
Output 1 0 H-z (Note 1) H-z (Note 2)
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MM80C95 * MM80C97 * MM80C98
Absolute Maximum Ratings(Note 3)
Voltage at Any Pin Operating Temperature Range Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline 700 mW 500 mW -0.3V to VCC + 0.3V -40C to +85C -65C to +150C
Power Supply Voltage (VCC) Lead Temperature (Soldering, 10 seconds)
18V 260C
Note 3: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) IOZ ICC VIN(1) VIN(0) VOUT(1) VOUT(0) Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Logical "1" Input Current Logical "0" Input Current Output Current in High Impedance State Supply Current Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage TTL INTERFACE VCC = 4.75V VCC = 4.75V VCC = 4.75V, IO = -1.6 mA VCC = 4.75V, IO = 1.6 mA OUTPUT DRIVE (Short Circuit Current) ISOURCE ISOURCE ISINK ISINK Output Source Current Output Source Current Output Sink Current Output Sink Current VCC = 5V, VIN(1) = 5V TA = 25C, VOUT = 0V VCC = 10V, VIN(1) = 10V TA = 25C, VOUT = 0V VCC = 5V, VIN(0) = 0V TA = 25C, VOUT = VCC VCC = 10V, VIN(0) = 0V TA = 25C, VOUT = VCC 20 mA 4.35 mA -20 mA -4.35 mA 0.4 V 2.4 VCC - 1.5 0.8 V V V VCC = 15V, VO = 15V VCC = 15V, VO = 0V VCC = 15V -1.0 VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 15V -1.0 0.005 -0.005 0.005 -0.005 0.01 15 1.0 4.5 9.0 0.5 1.0 1.0 3.5 8.0 1.5 2.0 V V V V V V V V A A A A A Parameter Conditions Min Typ Max Units
3
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MM80C95 * MM80C97 * MM80C98
AC Electrical Characteristics
TA = 25C, CL = 50 pF, unless otherwise noted. Symbol tpd0, tpd1 Parameter Propagation Delay Time to a Logical "0" or Logical "1" from Data Input to Output MM80C95, MM80C97 MM80C98 tpd0, tpd1 Propagation Delay Time to a Logical "0" or Logical "1" from Data Input to Output MM80C95, MM80C97 MM80C98 t1H, t0H
(Note 4)
Conditions Min Typ Max Units
VCC = 5V VCC = 10V VCC = 5V VCC = 10V
60 25 70 35
100 40 150 75
ns ns ns ns
VCC = 5V, CL = 150 pF VCC = 10V, CL = 150 pF VCC = 5V, CL = 150 pF VCC = 10V, CL = 150 pF
85 40 95 45
160 80 210 110
ns ns ns ns
Delay from Disable Input to High Impedance RL = 10k, CL = 5 pF State, (from Logical "1" or Logical "0") MM80C95 MM80C97 MM80C98 VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V 80 50 70 50 90 70 135 90 125 90 170 125 ns ns ns ns ns ns
tH1, tH0
Delay from Disable Input to Logical "1" Level RL = 10k, CL = 50 pF (from High Impedance State) MM80C95 MM80C96 MM80C98 VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V Any Input (Note 5) Any Output (Note 5) (Note 6) 120 50 130 60 120 50 5.0 11 60 200 90 225 110 200 90 ns ns ns ns ns ns pF pF pF
CIN COUT CPD
Input Capacitance Output Capacitance 3-STATE Power Dissipation Capacitance
Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: Capacitance is guaranteed by periodic testing. Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note AN-90.
AC Test Circuits and Switching Time Waveforms
tpd0, tpd1 t1H and tH1
CMOS to CMOS
t1H
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MM80C95 * MM80C97 * MM80C98
AC Test Circuits and Switching Time Waveforms
tH1
(Continued) t0H
t0H and tH0
tH0
Note: Delays measured with input tr, tf 20 ns.
Typical Performance Characteristics
Propagation Delay vs Load Capacitance tpd/pF vs Power Supply Voltage
N-Channel Output Drive at 25C
P-Channel Output Drive at 25C
5
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MM80C95 * MM80C97 * MM80C98
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
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MM80C95 * MM80C97 * MM80C98 3-STATE Hex Buffers * 3-STATE Hex Inverters
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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